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Power Supply IC Series for TFT-LCD Panels
5V Input Multi-channel System Power Supply IC
BD8179MUV
No.09035EBT04
Description The BD8179MUV is a system power supply IC for TFT panels. A 1-chip IC providing a total of three voltages required for TFT panels, i.e., source voltage, gate high-level, and gate low-level voltage, thus constructing a TFT panel power supply with minimal components required. Features 1) Step Up DC/DC Converter. 2) Incorporates 18V, 3.0A N-channel FET 3) Linear-Regulator Controllers for VGON and VGOFF 4) 5 channel Operational Amplifiers/150mA Output Short-Circuit Current 40V / s Slew Rate 5) Switching Frequency: 1200 kHz. 6) Gate Shading Function Included. 7) Protection Circuits 8) Over Current Protection 9) Timer Latch Mode Short Current Protection. 10) Thermal Shut Down. 11) Under Voltage Protection. 12) Over Voltage Protection 13) VQFN032V5050 Package Applications Liquid crystal TV, PC monitor, and TFT-LCD panel Absolute maximum ratings (Ta = 25) Parameter Power Supply Voltage VMAIN Voltage SUP Voltage DRVP Voltage DRVN Voltage SRC Voltage CTL Voltage Junction Temperature Power Dissipation Operating Temperature Range Storage Temperature Range Symbol VIN VMAIN VSUP VDRVP VDRVN VSRC VCTL Tjmax Pd Topr Tstg Limit 7 20 20 40 -30 40 7 150 4560 -4085 -55150 Unit V V V V V V V mW
* Reduced by 19.52 mW/ over 25, when mounted on a glass epoxy board. (4-layer 74.2 mm 74.2 mm 1.6 mm).
Operating Condition Parameter Power Supply Voltage VMAIN Voltage SUP Voltage DRVP Voltage DRVN Voltage SRC Voltage Symbol VIN VMAIN VSUP VDRVP VDRVN VSRC Limit Min. 2.6 8 Max. 5.5 18 18 38 -20 38 Unit V V V V V V
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1/12
2009.07 - Rev.B
BD8179MUV
Technical Note
Electrical Characteristics (Unless otherwise specified, VIN = 3.3V; VSUP = 12 V; VGON = 25 V; VGOFF = -6V; Ta = 25) 1 DC/DC CONVERTER CONTROLLER BLOCK Limit Parameter Symbol Unit Conditions Min. Typ. Max. [ ERROR AMPLIFIER BLOCK ] FB Input Bias Current Feed Back Voltage Comp Sink Current Comp Source Current [ LX BLOCK ] LX ON-Resistance LX Leak Current MAX Duty Cycle LX Current Limit [ INTERNAL SOFT START BLOCK ] Soft Start Delay Time tss 2. GATE-ON LINEAR REGULATOR CONTROLLER Parameter FBP Voltage FBP Input Bias Current Symbol VFBP IFBP Min. 1.225 3.25 Limit Typ. 1.25 0.1 5 Limit Min. 0.235 1 Typ. 0.25 0.1 5 Limit Min. 0 50 40 Limit Min. -8 1.2 VIN x 0.7 8 Typ. 15 -5 1.25 16.5 5 30 Max. -2 1.3 VIN x 0.3 25 Typ. 0 Max. VSUP Max. 0.265 10 Max. 1.275 10 ms Ron Ileak DMAX ILX 2.5 200 0 90 10 m A % A VLX=18V IFB VFB Ioi Ioo 1.221 1 -10 0.1 1.233 5 -5 1.245 10 -1 A V A A Buffer, No load VFB=1.5V VCOMP=0.5V VFB=1.0V VCOMP=0.5V
Unit V A mA Unit V A mA
Conditions
DRVP Current Limit IDRVP 1 3. GATE-OFF LINEAR REGULATOR CONTROLLER Parameter FBN Voltage FBN Input Bias Current DRVN Current Limit 4. OPERATIONAL AMPLIFIERS Parameter Input Offset Voltage Input Range DRIVE Current Symbol VFBN IFBN IDRVN
Conditions
Symbol Voff VRANGE Idrv
Unit mV V mA V/us
Conditions VPOS15 = 6V
Slew Rate SR 5. GATE SHADING CONTROLLER BLOCK Parameter DEL Start Period DEL Source Current DEL Threshold Voltage CTL Input Low Voltage CTL Input High Voltage CTL Input Current SRC ON Resistance DRN ON Resistance Symbol tdd Idls Vdls Vctll Vchlh Ictl RonSRC RonDRV
Unit ms A V V V A
Conditions
VCTL=3.3V
This product is not designed for protection against radioactive rays.
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2/12
2009.07 - Rev.B
BD8179MUV
Technical Note
Electrical Characteristics (Unless otherwise specified, VIN = 3.3V; VSUP = 12 V; VGON = 25 V; VGOFF = -6V; Ta = 25) 6. WHOLE DEVICE Limit Parameter Symbol Unit Conditions Min. Typ. Max. [ REFERENCE BLOCK ] Reference Voltage [ OSCILLATION BLOCK ] Oscillation Frequency Detect Voltage Detect Voltage Fault Delay Time [ DETECTOR BLOCK ] VFB OFF Threshold Voltage VFBP OFF Threshold Voltage VFBN OFF Threshold Voltage Vthfb Vthfbp Vthfpn 0.9 0.9 0.4 1.0 1.0 0.5 1.1 1.1 0.6 V V V FOSC Vuvlo Vovp Tscp 1020 2.25 18 1200 2.4 19 150 1380 2.55 20 kHz V V ms [ VIN UNDER VOLTAGE LOCK OUT BLOCK ] [ SUP OVER VOLTAGE LOCK OUT BLOCK ] [ SHORT CURRENT PROTECTION BLOCK ] VREF 1.231 1.25 1.269 V
This product is not designed for protection against radio active rays.
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3/12
2009.07 - Rev.B
BD8179MUV
Reference Data (Unless otherwise specified, Ta = 25, VIN=5V)
1000
Technical Note
3 2.5
2
1.5
Frequency[MHz]
100
DELAY TIME [ms]
2
IIN (mA)
1.5 1 0.5 0 0 1 2 3
VIN (V)
1
10
0.5
1
4
5
6
7
0 -40 10
Ta[]
0.1
60
0.001
0.01
0.1
1
DEL CAPACITOR [uF]
Fig.1 Supply Current (No switching)
94 92 90 88
Fig.2 Switching Frequency vs Temperature
1 0.8 0.6 0.4 VMAIN[%] 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 100 200 300 400 500
LX VIMAIN
Fig.3 Delay Time vs Capacitor
efficency[%]
86 84 82 80 78 76 0 100 200 300 400 500
Io[mA]
Io[mA]
Fig.4 Efficiency vs Output Current (VMAIN)
1 0.8 0.6 0.4
VGH[%]
VGL[%]
Fig.5 VMAIN Voltage Load Regulation
1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 20 40 60 80 100
Fig.6 Over Voltage Protect waveform
COM
0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Io[mA] 0 20 40 60 80 100
CTL
Io[mA]
Fig.7 Gate-ON Voltage Load Regulation
Fig.8 Gate-OFF Voltage Load Regulation
Fig.9 Gate Shading Output waveform
IN
OUT
IN
OUT
IN 300 100pF
OUT
IN 300 100pF
OUT
Fig.10 AMP Slew Rate (Rise)
Fig.11 AMP Slew Rate (Fall)
Fig.12 Start Up Sequence waveform
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4/12
2009.07 - Rev.B
BD8179MUV
Pin Assignments Diagram Block Diagram
VCN
Technical Note
VCP
COMP
VIN
VMAIN LX STEP-UP CONTROLLER
NEG5
POS5
OUT5
OUT4
FB
LX
IN
IN
FB
24 23 22 21 20 19 18 17 FBP DRVP FBN DRVN DEL CTL DRN COM 25 26 27 28 29 30 31 32 1 SRC 2 REF 3 AGND 4 PGND 5 OUT1 6 NEG1 7 POS1 8 OUT2 16 15 14 NEG4 POS4 SUP OUT3 POS3 BGND POS2 NEG2
COM SRC COMP
PGND
AGND VCP
BD8179MUV
13 12 11 10 9
DRVP GATE-ON CONTROLLER FBP DEL GATE SHADING CONTROLLER CTL DRN VCN VGON
DRVN GATE-OFF CONTROLLER SUP NEG1 OUT1 POS1 NEG2 OUT2 POS2 OP2 OP1 FBN VGOFF

REF
REF
NEG4

OP4
OUT4 POS4
OP3 OUT2 POS3

BGND
OP5 OUT5 POS5
NEG5
Pin Assignments
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name SRC REF AGND PGND OUT1 NEG1 POS1 OUT2 NEG2 POS2 BGND POS3 OUT3 SUP POS4 NEG4 Function Highside Input for Gate Shading switch Reference for VGOFF Ground Power Ground Operational Operational Operational Operational Operational Operational Ground Operational Operational Amplifier 3 Noninverting Input Amplifier 3 Output Amplifier 1 Output Amplifier 1 Inverting Input Amplifier 1 Noninverting Input Amplifier 2 Output Amplifier 2 Inverting Input Amplifier 2 Noninverting Input PIN NO. 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Pin Name OUT4 POS5 NEG5 OUT5 LX IN FB Operational Operational Operational Operational Function Amplifier 4 Output Amplifier 5 Noninverting Input Amplifier 5 Inverting Input Amplifier 5 Output
Nch Power MOS FET Drain and Switching Node Power Supply voltage Input Feedback Input for step up DC/DC
COMP Error Amplifier Compensation Point for step up DC/DC FBP DRVP FBN DRVN DEL CTL DRN COM Feedback Input for Gate-ON Linear-Regulator Gate-ON Linear-Regulator Base Drive Feedback Input for Gate-OFF Linear-Regulator Gate-OFF Linear-Regulator Base Drive Delay Input for Gate Shading Switch Control Input for Gate Shading Lowside Input for Gate Shading switch Gate Shading Output
Power Supply voltage Input for operational Amplifier Operational Operational Amplifier 4 Noninverting Input Amplifier 4 Inverting Input
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5/12
2009.07 - Rev.B
BD8179MUV
Technical Note
Block Function Step-up Controller A controller circuit for DC/DC boosting. The switching duty is controlled so that the feedback voltage FB is set to 1.233 V (typ.). A soft start operates at the time of starting. Gate-on Controller A controller circuit for the positive-side charge pump. The liner regulator controls so that the feedback voltage FBP will be set to 1.25 V (typ.). Gate-off Controller A controller circuit for the negative-side charge pump. The liner regulator controls so that the feedback voltage FBN will be set to 0.25 V (Typ.). Gate Shading Controller A controller circuit for MOS FET Switch The COM switching synchronize with CTL input. Start-up Controller A control circuit for the starting sequence. Controls to start in order of VCC VMAIN VGOFF/VGONVCOM REF A block that generates internal reference voltage. 1.25V (Typ.) is output. TSD/UVLO/OVP Thermal shutdown/Under-voltage lockout protection/circuit blocks. The thermal shutdown circuit is shut down at an IC internal temperature of 175C and reactivate at 160C. The under-voltage lockout protection circuit shuts down the IC when the VIN is 2.4 V (typ.) or below. The over-voltage lockout protection circuit shuts down the IC when the SUP is 19.0 V (typ.) or over. OP1OP5 Operational amplifier block Starting sequence VIN 2.4
VMAIN 3.25ms VGON
VGON/VGOFF VGOFF 15ms VDEL 1.25V
VCOM
UVLO released when VIN voltage reaches 2.4V Step up DCDC converter starts switching, and VGON and VGOFF starts. VDEL starts. VCOM ON when VDEL reaches 1.25V
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6/12
2009.07 - Rev.B
BD8179MUV
Technical Note
Under Voltage Lock Out (UVLO) The UVLO circuit compares the input voltage at IN with the UVLO threshold (2.4V rising, 2.2V falling, typ) to ensure the input voltage is high enough for reliable operation. The 200mV (typ) hysteresis prevents supply transients from causing a restart. Once the input voltage exceeds the UVLO rising threshold, startup begins. When the input voltage falls below the UVLO falling threshold, the controller turns off the main step-up regulator, turns off the linear-regulator outputs, and disables the Gate Shading controller. Thermal Shut Down (TSD) The TSD prevents excessive power dissipation from overheating the BD8179MUV. When the junction temperature exceeds Tj=175(Typ), a thermal sensor immediately activates. The fault protection, which shuts down all outputs except the reference, allowing the device to cool down. Once the device cools down by approximately 15 reactivate the device. Over Voltage Protection (OVP) The Step up DC/DC converter has OVP circuit. The OVP circuit compares the input Voltage at SUP with the OVP threshold (19V rising, 18.5V falling, Typ) to protect the step up DC/DC output exceed the absolute maximum voltage. Once the SUP Voltage exceeds the OVP rising threshold, turn off the main Step-up regulator. Then, the SUP Voltage falls bellow the OVP falling threshold,reactivate the main Step-Up regulator. Over Current Protection (OCP) The Step-Up DC/DC converter, linear-regulator and Operational Amplifier have OCP circuit respectively. The OCP circuit restricts to load current, when an OCP activated, one's own output only restricted. However, if the output continue to overload, the device is possible to activate thermal shutdown or short current protection. Timer Latch Mode Short Current Protection (SCP) BD8179MUV has SCP circuit feature to prevent the large current flowing when the output is shorted to GND. This function is monitoring VMAIN, VGON, and VGOFF Voltage and starts the timer when at least one of the outputs operating properly (when the output voltage was lower than expected). After 150ms (Typ.) of this abnormal state, the device will shutdown the all outputs and latch the state.
VMAIN FB

VGON FBP
150ms typ Counter
reset
all outputs shut down.
VGOFF FBN

Fig.13 SCP Block Diagram
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7/12
2009.07 - Rev.B
BD8179MUV
Technical Note
Selecting Application Components (1) Setting the Output L Constant The coil to use for output is decided by the rating current ILR and input current maximum value IINMAX of the coil. IINMAX + IL should not reach the rating value level L VCC IL Vo
IL
ILR IINMAX average current
Co
Fig.14 Coil Current Waveform
Fig. 15 Output Application Circuit Diagram
Adjust so that IINMAX +IL does not reach the rating current value ILR. At this time, IL can be obtained by the following equation. 1 Vcc Vo-Vcc 1 IL = [A] Here, f is the switching frequency. L Vcc f Set with sufficient margin because the coil value may have the dispersion of 30%. If the coil current exceeds the rating current ILR of the coil, it may damage the IC internal element. BD8179MUV uses the current mode DC/DC converter control and has the optimized design at the coil value. A coil inductance (L) of 4.7 H to 15 H is recommended from viewpoints of electric power efficiency, response, and stability. (2) Output Capacity Settings For the capacitor to use for the output, select the capacitor which has the larger value in the ripple voltage VPP allowance value and the drop voltage allowance value at the time of sudden load change. Output ripple voltage is decided by the following equation. 1 Vcc IL = ILMAX RESR + (ILMAX ) [V] Here, f is the switching frequency. VPP fCo Vo 2 Perform setting so that the voltage is within the allowable ripple voltage range. For the drop voltage during sudden load change; VDR, please perform the rough calculation by the following equation. I VDR = 10 us [V] Co However, 10 s is the rough calculation value of the DC/DC response speed. Please set the capacitance considering the sufficient margin so that these two values are within the standard value range. (3) Selecting the Input Capacitor Since the peak current flows between the input and output at the DC/DC converter, a capacitor is required to install at the input side. For the reason, the low ESR capacitor is recommended as an input capacitor which has the value more than 10 F and less than 100 m. If a capacitor out of this range is selected, the excessive ripple voltage is superposed on the input voltage, accordingly it may cause the malfunction of IC. However these conditions may vary according to the load current, input voltage, output voltage, inductance and switching frequency. Be sure to perform the margin check using the actual product.
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8/12
2009.07 - Rev.B
BD8179MUV
Technical Note
(4) Setting RC, CC of the Phase Compensation Circuit In the current mode control, since the coil current is controlled, a pole (phase lag) made by the CR filter composed of the output capacitor and load resistor will be created in the low frequency range, and a zero (phase lead) by the output capacitor and ESR of capacitor will be created in the high frequency range. In this case, to cancel the pole of the power amplifier, it is easy to compensate by adding the zero point with CC and RC to the output from the error amp as shown in the illustration. Open loop gain characteristics
Fp =
A fp(Min) fp(Max) Gain [dB] lOUTMin lOUTMax fz(ESR) 0
1 2 RO CO 1 2 ESR CO
[Hz] [Hz]
fz(ESR) =
Pole at the power amplification stage When the output current reduces, the load resistance Ro increases and the pole frequency lowers.
fp(Min) = 1 2 ROMax CO 1 fz(Max) = 2 ROMin CO [Hz]at light load [Hz]at heavy load
0 Phase [deg] -90
Error amp phase compensation characteristics
A Gain [dB] 0
Phase [deg]
0 -90
Zero at the power amplification stage When the output capacitor is set larger, the pole frequency lowers but the zero frequency will not change. (This is because the capacitor ESR becomes 1/2 when the capacitor becomes 2 times.)
fp(Amp.) = 1 2 Rc Cc
[Hz]
Fig. 16 Gain vs Phase
L Vo
VCC
Cin COMP Rc
Vcc,PVcc SW
ESR
Ro
Co
GND,PGND
Cc
Fig. 17 Application Circuit Diagram It is possible to realize the stable feedback loop by canceling the pole fp(Min.), which is created by the output capacitor and load resistor, with CR zero compensation of the error amp as shown below. fz(Amp.) = fp(Min.) 1 2 Rc Cc 1 2 Romax C [Hz]
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9/12
2009.07 - Rev.B
BD8179MUV
Technical Note
(5) Design of the Feedback Resistor Constant Refer to the following equation to set the feedback resistor. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than a 10 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.4 A(Typ.) in the internal error amplifier. Reference voltage 1.233 V 1.233 [V] Vo R1
23
VMAIN =
R1 + R2 R2
ERR
R2
FB
(6) Positive-side Charge Pump Settings BD8179MUV incorporates a charge pump controller, thus making it possible to generate stable gate voltage. The output voltage is determined by the following formula. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than a 10k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.4 A (Typ.) in the internal error amp.
VGON Reference voltage 1.25 V R3
25
VGON =
R3 + R4 R4
1.25
[V]
C3 1000 pF to 4700 pF R4
FBP
ERR
In order to prevent output voltage overshooting, add capacitor C3 in parallel with R3. The recommended capacitance is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate. By connecting capacitance to the DEL, a rising delay time can be set for the positive-side charge pump. The delay time is determined by the following formula. Delay time of charge pump block t DELAY t DELAY = ( CDEL 1.25 )/5 A [s] Where, CDEL is the external capacitance. (7) Negative-side Charge Pump Settings BD8179MUV incorporates a charge pump controller for negative voltage, thus making it possible to generate stable gate voltage. The output voltage is determined by the following formula. As the setting range, 10 k to 330 k is recommended. If the resistor is set lower than a 10 k, it causes the reduction of power efficiency. If it is set more than 330 k, the offset voltage becomes larger by the input bias current 0.4 A (Typ.) in the internal error amp. VGOFF C5 VGOFF = R5 R6 1.0 + 0.25 V [V] 1000 pF to 4700 pF R6 R5 27 FBN 0.25 V
ERR
2 REF 1.25 V
The delay time is internally fixed at 200 us. In order to prevent output voltage overshooting, insert capacitor C5 in parallel with R5. The recommended capacitance is 1000 pF to 4700 pF. If a capacitor outside this range is inserted, the output voltage may oscillate.
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10/12
2009.07 - Rev.B
BD8179MUV
Technical Note
Notes for use 1) Absolute maximum ratings Use of the IC in excess of absolute maximum ratings such as the applied voltage or operating temperature range may result in IC damage. Assumptions should not be made regarding the state of the IC (short mode or open mode) when such damage is suffered. A physical safety measure such as a fuse should be implemented when use of the IC in a special mode where the absolute maximum ratings may be exceeded is anticipated. 2) GND potential Ensure a minimum GND pin potential in all operating conditions. 3) Setting of heat Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 4) Pin short and mistake fitting Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by the presence of a foreign object may result in damage to the IC. 5) Actions in strong magnetic field Use caution when using the IC in the presence of a strong magnetic field as doing so may cause the IC to malfunction. 6) Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. 7) Ground wiring patterns When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the application's reference point so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring patterns of any external components. 8) This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create a variety of parasitic elements.For example, when the resistors and transistors are connected to the pins as shown in Fig. 18, a parasitic diode or a transistor operates by inversing the pin voltage and GND voltage. The formation of parasitic elements as a result of the relationships of the potentials of different pins is an inevitable result of the IC's architecture. The operation of parasitic elements can cause interference with circuit operation as well as IC malfunction and damage. For these reasons, it is necessary to use caution so that the IC is not used in a way that will trigger the operation of parasitic elements, such as the application of voltages lower than the GND (P board) voltage to Resistor Transistor (NPN) (Pin B) input and output pins. B
(Pin A)

(Pin B)
C

GND
E
B
C
E GND Parasitic elements
P+ N N P
P
N P+ N Parasitic element N P N P substrate Parasitic elements GND GND P P N (Pin A)
GND
Parasitic element
Fig.18 Example of a Simple Monolithic IC Architecture
9) Overcurrent protection circuits An overcurrent protection circuit designed according to the output current is incorporated for the prevention of IC destruction that may result in the event of load shorting. This protection circuit is effective in preventing damage due to sudden and unexpected accidents. However, the IC should not be used in applications characterized by the continuous operation or transitioning of the protection circuits. At the time of thermal designing, keep in mind that the current capability has negative characteristics to temperatures. 10) Thermal shutdown circuit This IC incorporates a built-in thermal shutdown circuit for the protection from thermal destruction. The IC should be used within the specified power dissipation range. However, in the event that the IC continues to be operated in excess of its power dissipation limits, the attendant rise in the chip's temperature Tj will trigger the thermal shutdown circuit to turn off all output power elements. The circuit automatically resets once the chip's temperature Tj drops. Operation of the thermal shutdown circuit presumes that the IC's absolute maximum ratings have been exceeded. Application designs should never make use of the thermal shutdown circuit. 11) Testing on application boards At the time of inspection of the installation boards, when the capacitor is connected to the pin with low impedance, be sure to discharge electricity per process because it may load stresses to the IC. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure, and use similar caution when transporting or storing the IC.
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11/12
2009.07 - Rev.B
BD8179MUV
Ordering part number
Technical Note
B
D
8
Part No.
1
7
9
M
U
V
-
E
2
Part No.
Package MUV:VQFN032V5050
Packaging and forming specification E2: Embossed tape and reel
VQFN032V5050
5.00.1
5.0 0.1

Tape Quantity Direction of feed Embossed carrier tape 2500pcs E2
The direction is the 1pin of product is at the upper left when you hold
1PIN MARK
1.0MAX
S
+0.03 0.02 -0.02 (0.22)
( reel on the left hand and you pull out the tape on the right hand
)
0.08 S C0.2
0.4 0.1
32
3.40.1
1 8 9
25 24 17
16
0.75 0.5
3.4 0.1
+0.05 0.25 -0.04
1pin
Direction of feed
(Unit : mm)
Reel
Order quantity needs to be multiple of the minimum quantity.
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12/12
2009.07 - Rev.B
Notice
Notes
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